1. Field of the Invention
This invention relates to a method for fabricating semiconductor devices and particularly to improvements in a method for forming a base electrode lead-out region for a transistor in a bipolar type semiconductor integrated circuit device and in a method for forming a base current feeding resistor to be connected to the base of said transistor.
2. Description of the Prior Art
Generally, a transistor in a bipolar type semiconductor integrated circuit device is formed in an electrically separated island by such a method as pn junction isolation process, oxide isolation process using selective oxidation process, or triple diffusion process. Herein will be described a method of forming npn transistors by oxidation isolation process. In a bipolar type semiconductor integrated circuit device, its components are, generally, transistors, diodes and resistors, said diodes being made by the same fabricating process as used for said transistors. Thus, herein will be described a semiconductor device in the form of a combination of transistors and resistors, i.e., a semiconductor device shown in FIG. 1 which has a transistor Tr with a base current feeding resistor R connected to its base B.
FIGS. 2A through 2E are views, showing conventional main fabrication steps, of a transistor with a resistor connected to its base. A conventional method for fabrication will now be described with reference to FIGS. 2A through 2E.
First, as shown in FIG. 2A, in a p-type silicon semiconductor substrate 1 of low impurity concentration (i.e., p.sup.- -type) is selectively formed a first and a second high impurity concentration n type (n.sup.+ -type) layers 2a and 2b serving as collector buried layers, on which an n.sup.- -type epitaxial layer 3 is grown.
Next, as shown in FIG. 2B, a pad oxide film 101 and a nitride film 201 are successively formed on the n.sup.- -type epitaxial layer 3, and the nitride film 201 is patterned into a predetermined form. With said patterned nitride film 201 used as a mask, selective oxidation is applied to form a thick isolation oxide film 102 which surrounds a transistor forming region and a resistor forming region. In this oxidation process, a p-type channel-cutting layer 4 is simultaneously formed under the isolation oxide film 102. As a result, the transistor forming regions and the resistor forming regions are respectively formed in predetermined areas. For the sake of convenience of description, the n.sup.- -type epitaxial layer 3 which forms the collector region of the transistor will be hereinafter referred to as a first n.sup.- -type layer 3a and the n.sup.- -type epitaxial layer 3 for the resistor region as a second epitaxial layer 3b.
Then, as shown in FIG. 2C, the nitride film 201 used as a mask for said selective oxidation is removed together with the pad oxide film 101, and then oxide films 103 serving as protective films for ion implantation are formed on the n.sup.- -type epitaxial layers 3a and 3b. Subsequently, with a photoresist film (which, at this stage, is not shown) used as a mask, a p.sup.- -type layer 5 serving as an external base layer is formed such that one side wall thereof contacts the isolation oxide film 102 which isolates the transistor and the resistor regions from each other. Further, the photoresist film used as the mask is then removed and photoresist films 301 of predetermined shape are formed. Then, with photoresist films 301 used as masks, ion implantation is effected such that in the surface of the first n.sup.- -type epitaxial layer 3a is formed a p-type layer 6 serving as an active base region with one side wall thereof contacting the external base layer 5 and that in the surface of second n.sup.- -type epitaxial layer 3b is formed a p-type layer 9 serving as a resistor region.
Subsequently, as shown in FIG. 2D, the photoresist film 301 is removed and a passivation film 401 generally made of phosphosilicate glass (PSG) is deposited on the entire surface, and a heat treatment is performed for annealing of the ion-implanted external base layer 5 and active base region 6 as well as for thermal shrinking of the PSG film 401, thereby forming the external base layer 5 and the active base layer 6 in intermediate state and resistor region 9. Then, openings 70 and 80 are formed in predetermined regions of the PSG film 401, and ion implantation is effected through the openings 70 and 80, whereby in a portion of the the surface of the active base layer 6 is formed an n.sup.+ -type layer 7 serving as an emitter layer and in a portion of the surface of the first n.sup.- -type epitaxial layer 3a is formed an n.sup.+ -type layer 8 serving as a collector electrode lead-out layer.
Then, as shown in FIG. 2E, each ion-implanted layer is annealed to complete the external base layer 5, active base region 6 and resistor region 9 while the emitter region 7 and the collector electrode lead-out layer 8 are formed, and then an opening 50 for leading out the base electrode and openings 91 and 92 for leading out the resistor electrodes are formed. On the bottom of each of the openings 50, 70, 80, 91 and 92 is formed a metal silicide film 501 for preventing electrode penetration (prevention of reaction between the electrode material and the semiconductor substrate). The metal silicide films 501 are formed, e.g., of platinum silicide Pt-Si or palladium silicide Pd-Si. Then, a low resistance metal, such as aluminum Al, is used to form a base electrode interconnection 12, an emitter electrode interconnection 10, a collector electrode interconnection 11, a base-resistor interconnection 13 and a resistor electrode interconnection 14.
FIG. 3 is a plan pattern view of the transistor and resistor formed by abovesaid method shown in FIGS. 2A through 2E. In FIG. 3, the base electrode interconnection 12, the emitter electrode interconnection 10, and the collector electrode interconnection 11 are disposed parallel to each other and are electrically connected to the external base region 5, the emitter region 7, and the collector electrode lead-out region 8 through the contact holes 50, 70, and 80, respectively. Problems associated with the prior art semiconductor device will now be described with reference to FIG. 3.
The frequency characteristic of transistors depends on such factors as base-collector capacitance and base resistance and these factors must be reduced in order to improve the frequency characteristic. In the aforesaid construction, the p.sup.+ -type external base layer 5 has been provided to reduce the base resistance; however, this has the drawback of increasing the base area and hence the base-collector capacitance. Further, the base resistance also depends on the distance D1 between the emitter region 7 and the base electrode opening 50. In the conventional construction, the distance D1 is the sum of the spacing between the base electrode interconnection 12 and the emitter electrode interconnection 10 and the distances by which the electrode interconnections 9 and 10 protrude beyond the openings 50 and 70, respectively. Even if photoetching accuracy is improved to reduce the spacing of the electrode interconnections, said protrusion distances cannot be eliminated; thus, there has been a limit to the reduction of the distance D1.
Further, since the resistor region 9 connected to the base of the transistor is formed of diffusion resistance, it is necessary to isolate the transistor and the resistor regions from each other by the isolation oxide film 102, thus making it difficult to increase the degree of integration. Furthermore, since the resistor region 9 is isolated by the pn junction, there is created a capacitance which forms a cause of degradation of frequency characteristic.
Further, the base region between the emitter layer 7 and the isolation oxide film boundary A shown in FIG. 3 is an inactive region, which increases the base-emitter capacitance. For elimination of this inactive region, there is a method using a walled-emitter construction in which the emitter layer 7 contacts the isolation oxide film. Even this method, however, encounters various drawbacks.
FIGS. 4A through 4C are views, shown in the order of fabrication steps, of a portion of a section taken along the line X--X in FIG. 3. Problems of the conventional walled emitter construction will now be described with reference to FIGS. 4A through 4C.
FIG. 4A shows a state in which for the formation of the base region, a p-type impurity such as boron has been implanted with the photoresist film 301 serving as a mask. Then, to form a contact hole, it is necessary to remove the oxide film 103 on the emitter region 7. However, in this walled-emitter construction, as shown in FIG. 4B, the boundary A of the isolation oxide film 102 is overetched during removal of the oxide film, so that the emitter region is deepened, as shown at the portion B in FIG. 4C. As a result, controllability of current amplification rate is degraded and there is the increased danger of a short-circuit taking place between the emitter and the collector at the portion B shown in FIG. 4C.
Further, double base construction, as shown in FIG. 5, is often used as a countermethod for reducing the base resistance. In the conventional method, however, there is a drawback that the provision of a base electrode lead-out region results in an increase in the size of the base region, leading to an increase in the base-collector capacitance.
Further, in the conventional method, the emitter-base junction is located deeper than the surface of the external base region, resulting in a drawback that current amplification factor depends more on electric current. That is, there is a problem that in a small level current region, electric current is absorbed in the interfaces (such as one between the emitter and the external base region) through recombination of electric charges and the like, whereby controllability of current amplification factor is degraded.
The prior arts concerning the present invention are as follows:
(1) S konaka et al., "A 30 ps Bipolar IC Using Self-Aligned Process Technology," Extended Abstract of the 16th Conference on Solid State Devices and Materials, 1984, pp 209-212;
(2) N Oh-uchi et al., "A New Self-Aligned Transistor Structure for High Speed and Low-Power Bipolar LSI's," Proceedings of the IEEE International Electron Devices Meeting, December 1983, pp 55-58; and
(3) D. D. Tang et al., "Subnanosecond Self-Aligned I.sup.2 L/MTL Circuits," IEEE Transaction on Electron Devices, Vol. ED-27, No. 8, August 1980.
The prior art (1) discloses a method for self-alignedly forming a base and emitter by using a single mask.
The prior art (2) discloses a method for forming an emitter of substantially the same area as that of the base region self-alignedly with respect to the isolation oxide region and the base region by surrounding the active region with the isolation oxide region and using a selective growth method.
The prior art (3) discloses a method for electrically isolating the base electrode interconnection and the emitter electrode interconnection from each other by leaving only the oxide film on a polysilicon side wall serving as an electrode interconnection through application of anisotropic etching.